Power Optimization of System-Level Address Buses based on Software Pro ling

The paper aims at de ning a methodology for the optimization of the switching power related to the processor-to memory communication on system-level buses. First, a methodology to pro le the switching activity related to system-level buses has been de ned, based on the tracing of benchmark programs running on the Sun SPARC V8 architecture. The bus traces have been analyzed to identify temporal correlations between consecutive patterns. Second, a framework has been set up for the design of high-performance encoder/decoder architectures to reduce the transition activity of the system-level buses. Novel bus encoding schemes have been proposed, whose performance has been compared with the most widely adopted power-oriented encodings. The experimental results have shown that the proposed encoding techniques provide an average reduction in transition activity up to 74:11% over binary encoding for instruction address streams. The results indicate the suitability of the proposed techniques for high-capacitance wide buses, for which the power saving due to the transition activity reduction is not o set by the extra power dissipation introduced in the system by the encoding/decoding logic.